The present disclosure relates in general to integrated circuit manufacturing, and more particularly to a system and method to optimize critical dimension uniformity in manufacturing of integrated circuits by using a sacrificial twin mask.
In integrated circuit manufacturing technology, a resist layer is typically applied to a semiconductor wafer surface, followed by an exposure of the resist through a mask (e.g., a reticle or photomask). A post-exposure baking process is then performed to alter physical properties of the resist for subsequent processing. An after-development inspection (ADI) is then performed to inspect the critical dimension (CD) and profile of the exposed resist using a scanning electron microscope (SEM) to determine whether it conforms to a specification. If the resist is within specification, a pattern is etched or transferred and the resist is stripped. An after-etching inspection (AEI) is then performed on the wafer.
Traditional SEM inspection, however, becomes a bottleneck for providing accurate and repeatable CD and profile analysis due to electron charging effects that not only limit the accuracy and repeatability of CD metrology, but also cause damage at the measurement area. In response, an optical critical dimension (OCD) method is often used instead of SEM inspection. OCD can detect CD information including CD profile and wafer film thickness. OCD also has much less noise than SEM and the sampling ratio of OCD is more accurate than the sampling ratio of SEM. Thus, OCD provides more consistent and comprehensive CD information than SEM.
Both SEM and OCD may be used in after-development inspection and after-etching inspection to optimize CD uniformity. With existing SEM and OCD tools, inter-field critical dimension uniformity may be optimized. Inter-field CD uniformity optimization may be obtained by examining the die-to-die CD difference between a plurality of dies on a wafer. For example, inter-field CD uniformity optimization may be performed over 80 die to improve the quality of selected measurement points of a wafer surface area.
In addition to inter-field optimization, intra-field CD uniformity optimization may be performed with existing SEM and OCD tools. Intra-field CD uniformity optimization may be performed by examining CD differences within a die or field of the wafer. However, due to the large grating size of an OCD pattern, such as 60×60 um, the OCD pattern may not distribute uniformly in the chip and the sampling size is limited. In addition, the OCD pattern may not be used on some devices, such as a static random access memory (SRAM) cell. Thus, intra-field CD uniformity optimization is limited by the location of the OCD pattern and the number of OCD samplings that can be performed by a scanner.
Therefore, a need exists for a method and system for optimizing intra-field CD uniformity, such that intra-field CD uniformity optimization is not limited by the grating size or the location of device regions.